【verilog】模十计数器

前言

进行 FPGA 模十计数器 实验

• 仿真结果
  

代码

• 主代码

// module
module count(
	clk,
	rst_n,
	count,
	clk1,
	led
	);


// def io
input clk;
input rst_n;
output reg [3:0] count;
output reg clk1;
output reg [7:0] led;

// always@ part, or main()
always @(posedge clk or negedge rst_n)
begin 
	if (~rst_n)

		begin
			count <= 4'b0000;
			clk1 <= 1'b0;
		end

	else if (count < 4'b0100)
		begin
			count <= count + 1;
			clk1 <= 1'b0;
		end

	else if (count < 4'b1001)
		begin
			count <= count + 1;
			clk1 <= 1'b1;
		end

	else if (count == 4'b1001)
		begin
			count <= 4'b0000;
			clk1 <= 1'b0;
		end
	
// end of whole begin
end




// --------------------------------------- always @ count --------------------------------------- //
always @(count) // todo: write the counter part
begin
	case(count)
		4'd0: led <= 8'b0000_0001;
		4'd1: led <= 8'b0000_0010;
		4'd2: led <= 8'b0000_0100;
		4'd3: led <= 8'b0000_1000;
		4'd4: led <= 8'b0001_0000;
		4'd5: led <= 8'b0010_0000;
		4'd6: led <= 8'b0100_0000;
		4'd7: led <= 8'b1000_0000;
		4'd8: led <= 8'b1111_1111;
		4'd9: led <= 8'b0000_0000;

		// default
		default: led <= 8'b0000_0000;
	endcase
end

endmodule

• 测试代码

`timescale 1ns/1ns

// module
module count_tst();
	// distribute value & name
	reg clk;
	reg rst_n;

	wire [3:0] count;
	wire clk1;
	wire [7:0] led;
	
	parameter period = 2;
	
	// init
	initial begin
		clk = 1'b0;
		rst_n = 1'b0;
		
		// delay
		#20 rst_n = 1'b1;
	end

	always
	begin
		#(period/2) clk = ~clk;
	end

	count u0(
		.clk(clk),
		.rst_n(rst_n),
		.count(count),
		.clk1(clk1),
		.led(led)
		);

endmodule