Fsm serialdata

现在您有了一个有限状态机，可以识别串行比特流中何时正确接收字节，添加一个数据路径，输出正确接收的数据字节。当done为1时，out_byte必须有效，否则为not。
请注意，串行协议首先发送最低有效位。

此题，注意两点

1、像Fsm ps2data 例题输出接收到的三个字节一样，输出赋值必须在时序逻辑中实现，而且必须在next_state 状态下。

2、输入bit存储在高位中，所以赋值应写为 a<= {in,a[7:1]},即右移一位。

module top_module(
    input clk,
    input in,
    input reset,    // Synchronous reset
    output [7:0] out_byte,
    output done
); //

   parameter IDEL    =   5'd00001,
    		  start  =   5'd00010,
    		  data   =   5'd00100,
    		  stop   =   5'd01000,
              err    =   5'd10000;
    reg[4:0] state,next_state;
    reg [4:0] time11;
    reg[7:0] mid;
    always@(posedge clk)begin
        if(reset)
            time11<= 0;
        else begin
            if(next_state == data)
                time11 <= time11+1;
            else 
                time11 <= 0;
           end
    
    end
    always@(posedge clk)begin
        if(reset)
            state <= IDEL;
        else
            state <= next_state;
     end
    always @(*)begin
        case(state)
            IDEL:  next_state =    in?  IDEL:start;
            start : next_state = data;
            data : next_state =  (time11==8)? (in? stop : err): data;
        	stop: next_state =   in? IDEL: start;
            err :  next_state = in?IDEL:err;
            default : next_state = IDEL;
        endcase
    
    end
    
    always@(posedge clk)begin
        if(reset)
            mid<= 8'd0;
        else
            case(next_state)
                data:mid <= {in,mid[7:1]};
                default : mid <= mid;
            endcase    
    end
    assign done = (state == stop);
    assign out_byte = (state == stop)? mid:0;
endmodule