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Vivado 编译（单核性能对比+高性能迷你主机+Ubuntu20.04/22.04安装与区别+20.04使用远程命令）

article 2024/12/24 4:10:49

1. 简介

2. 单核性能对比

2.1 PassMark

2.2 geekbench

2.3 CPU-7

2.4 选择 UM790 pro

3. Ubuntu 22.04 物理机

3.1 安装 Ubuntu 22.04

3.2 安装 Vitis 2022.1

3.3 缺点

4. Ubuntu 20.04 物理机

4.1 安装 Ubuntu 20.04

4.2 实用命令

4.2.1 文件管理器

4.2.2 控制中心

4.2.3 磁盘管理器

4.2.4 打开默认浏览器

4.2.5 系统监视器

4.2.6 终端

5. 性能测试

6. 总结

1. 简介

选购一款专用于 Vitis 和 Vivado 开发的主机，Vivado 的编译速度很大程度上取决于 CPU 的单核性能，尤其是在布线和综合阶段，最终选择一款迷你主机，不考虑使用独显，核性数一般即可。

按照 Single Thread Performance 对比即可，挑选一款最佳性价比产品。

对比 Ubuntu 22.04 和 Ubuntu 20.04 运行 Vivado 的兼容性。

2. 单核性能对比

2.1 PassMark

PassMark CPU Benchmarks - Single Thread Performancehttps://www.cpubenchmark.net/singleThread.html

Intel i5-10500 CPU @ 3.10GHz Tb 4.5GHz：Not on the list

Intel i7-1165G7 CPU @2.80GHz Tb 4.7GHz：Not on the list

Intel i7-11800H CPU @ 2.30GHz Tb 4.6GHz：Not on the list

Intel i7-13700 CPU @ 2.10GHz Tb 5.2GHz：4116

AMD R9 7940HS @ 4.0GHz Tb 5.2GHz：3956

Intel i9-14900K CPU @ 3.2GHz Tb 6GHz：4732

2.2 geekbench

Processor Benchmarks - Geekbenchhttps://browser.geekbench.com/processor-benchmarks

Intel i5-10500 CPU @ 3.10GHz Tb 4.5GHz：1526

Intel i7-1165G7 CPU @2.80GHz Tb 4.7GHz：1740

Intel i7-11800H CPU @ 2.30GHz Tb 4.6GHz：1900

Intel i7-13700 CPU @ 2.10GHz Tb 5.2GHz：2653

AMD R9 7940HS @ 4.0GHz Tb 5.2GHz：2460

Intel i9-14900K CPU @ 3.2GHz Tb 6GHz：3079

2.3 CPU-7

单核性能排名CPU天梯图，包含Intel Core2, Intel Core2 Quad和AMD Phenom四核处理器,ZHAOXIN-cpu7网比较了具有多个内核的Intel Xeon CPU，Intel Core i7 / i9 CPU，AMD Ryzen / Threadripper CPU和AMD Epyc的性能。英特尔(Intel)处理器与AMD芯片-找出最适合您的新游戏平台或服务器的CPU性能！完整cpu天梯图https://www.cpu7.com/single/thread.html

Intel i5-10500 CPU @ 3.10GHz Tb 4.5GHz：2765

Intel i7-1165G7 CPU @2.80GHz Tb 4.7GHz：2828

Intel i7-11800H CPU @ 2.30GHz Tb 4.6GHz：3091

Intel i7-13700 CPU @ 2.10GHz Tb 5.2GHz：4143

AMD R9 7940HS CPU @ 4.0GHz Tb 5.2GHz：4013

Intel i9-14900K CPU @ 3.2GHz Tb 6GHz：4780

2.4 选择 UM790 pro

我选择的配置：

AMD R9 7940HS
32G DDR5-5600
1TB M2-2280 PCIE4.0

图片来自铭凡官网。

3. Ubuntu 22.04 物理机

3.1 安装 Ubuntu 22.04

1）安装 Ubuntu 22.04

安装 Ubuntu 后，首先安装 SSH，并设置好 IP 地址，后续要用到。

sudo apt update
sudo apt install openssh-server

2）upgrade

sudo apt update
sudo apt upgrade

3）解决黑屏

运行 upgrade 后，重启会出现显示器黑屏的情况，但可以 ping 通，也可以通过 SSH 连接。风扇似乎也在全速运行。

sudo nano /etc/default/grub

找到对应位置，添加如下内容：

GRUB_CMDLINE_LINUX_DEFAULT="quiet splash nomodeset" // 这里添加 nomodeset
GRUB_CMDLINE_LINUX="rw" //这里需要填写为rw

使 grub 配置生效，并重启：

sudo update-grub
sudo reboot

3.2 安装 Vitis 2022.1

1）安装必要的库

sudo apt install libncurses5

运行 AppImage 格式的应用程序需要安装如下库：

sudo apt install libfuse2

2）修改 /opt 权限

sudo chmod 777 /opt

3）运行安装程序

./xsetup

如果跳过了 3.1-(4)，虽然安装过程不会报错，但是运行 vivado，则会报错：

>> vivado
---
application-specific initialization failed: couldn't load file "librdi_commontasks.so": libtinfo.so.5: cannot open shared object file: No such file or directory

4）安装 JTAG 驱动

cd /opt/Xilinx/Vivado/2022.1/data/xicom/cable_drivers/lin64/install_script/install_drivers/
sudo ./install_drivers.sh

3.3 缺点

无法安装 xrt 2022.1，导致不能使用无法运行自定义 DPU Overlay。

放弃 Ubuntu 22.04 + Vivado 2022.1 组合。

4. Ubuntu 20.04 物理机

4.1 安装 Ubuntu 20.04

步骤和 Ubuntu 22.04 一致，无需解决黑屏问题。

参考如下博客安装：

Vitis AI 基础配置（安装VMware+ubuntu 20.04+必要软件）_vitis ai安装-CSDN博客

4.2 实用命令

在 MobaXTerm 的 SSH 中，直接运行如下命令，可实现 X11 转发，在 Windows 窗口中直接显示 Ubuntu 20.04 的内容，非常方便。

4.2.1 文件管理器

>> nautilus

直接打开了最大化的页面，而且无法修改窗口大小。

4.2.2 控制中心

>> gnome-control-center

4.2.3 磁盘管理器

>> gnome-disks

4.2.4 打开默认浏览器

>> gnome-www-browser

4.2.5 系统监视器

>> gnome-system-monitor

4.2.6 终端

>> gnome-terminal

5. 性能测试

使用官方脚本，构建一个 DPU 工程。

CPU 大部分时间都是单核在在拉满，其余核心都在等待。

用时统计时如下：

[23:43:11] Run vpl: Step create_project: Started
Creating Vivado project.
[23:43:14] Run vpl: Step create_project: Completed
[23:43:14] Run vpl: Step create_bd: Started
[23:43:18] Run vpl: Step create_bd: Completed
[23:43:18] Run vpl: Step update_bd: Started
[23:43:18] Run vpl: Step update_bd: Completed
[23:43:18] Run vpl: Step generate_target: Started
[23:43:36] Run vpl: Step generate_target: Completed
[23:43:36] Run vpl: Step config_hw_runs: Started
[23:43:38] Run vpl: Step config_hw_runs: Completed
[23:43:38] Run vpl: Step synth: Started
[23:44:08] Block-level synthesis in progress, 0 of 20 jobs complete, 8 jobs running.
[23:44:38] Block-level synthesis in progress, 7 of 20 jobs complete, 8 jobs running.
[23:45:08] Block-level synthesis in progress, 15 of 20 jobs complete, 5 jobs running.
[23:45:38] Block-level synthesis in progress, 19 of 20 jobs complete, 1 job running.
[23:46:08] Block-level synthesis in progress, 19 of 20 jobs complete, 1 job running.
[23:46:38] Block-level synthesis in progress, 19 of 20 jobs complete, 1 job running.
[23:47:08] Block-level synthesis in progress, 19 of 20 jobs complete, 1 job running.
[23:47:38] Block-level synthesis in progress, 19 of 20 jobs complete, 1 job running.
[23:48:09] Block-level synthesis in progress, 19 of 20 jobs complete, 1 job running.
[23:48:39] Block-level synthesis in progress, 19 of 20 jobs complete, 1 job running.
[23:49:09] Block-level synthesis in progress, 19 of 20 jobs complete, 1 job running.
[23:49:39] Block-level synthesis in progress, 20 of 20 jobs complete, 0 jobs running.
[23:50:09] Run vpl: Step synth: Completed
[23:50:09] Run vpl: Step impl: Started
[23:51:10] Finished 2nd of 6 tasks (FPGA linking synthesized kernels to platform). Elapsed time: 00h 08m 02s

[23:51:10] Starting logic optimization..
[23:51:40] Phase 1 Retarget
[23:51:40] Phase 2 Constant propagation
[23:51:40] Phase 3 Sweep
[23:51:40] Phase 4 BUFG optimization
[23:51:40] Phase 5 Shift Register Optimization
[23:51:40] Phase 6 Post Processing Netlist
[23:52:10] Finished 3rd of 6 tasks (FPGA logic optimization). Elapsed time: 00h 01m 00s

[23:52:10] Starting logic placement..
[23:52:10] Phase 1 Placer Initialization
[23:52:10] Phase 1.1 Placer Initialization Netlist Sorting
[23:52:10] Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
[23:52:10] Phase 1.3 Build Placer Netlist Model
[23:52:40] Phase 1.4 Constrain Clocks/Macros
[23:52:40] Phase 2 Global Placement
[23:52:40] Phase 2.1 Floorplanning
[23:52:40] Phase 2.1.1 Partition Driven Placement
[23:52:40] Phase 2.1.1.1 PBP: Partition Driven Placement
[23:53:10] Phase 2.1.1.2 PBP: Clock Region Placement
[23:53:10] Phase 2.1.1.3 PBP: Discrete Incremental
[23:53:10] Phase 2.1.1.4 PBP: Compute Congestion
[23:53:10] Phase 2.1.1.5 PBP: Macro Placement
[23:53:10] Phase 2.1.1.6 PBP: UpdateTiming
[23:53:10] Phase 2.1.1.7 PBP: Add part constraints
[23:53:10] Phase 2.2 Update Timing before SLR Path Opt
[23:53:10] Phase 2.3 Post-Processing in Floorplanning
[23:53:10] Phase 2.4 Global Placement Core
[23:54:10] Phase 2.4.1 Physical Synthesis In Placer
[23:54:41] Phase 3 Detail Placement
[23:54:41] Phase 3.1 Commit Multi Column Macros
[23:54:41] Phase 3.2 Commit Most Macros & LUTRAMs
[23:54:41] Phase 3.3 Small Shape DP
[23:54:41] Phase 3.3.1 Small Shape Clustering
[23:54:41] Phase 3.3.2 Flow Legalize Slice Clusters
[23:54:41] Phase 3.3.3 Slice Area Swap
[23:54:41] Phase 3.3.3.1 Slice Area Swap Initial
[23:55:11] Phase 3.4 Re-assign LUT pins
[23:55:11] Phase 3.5 Pipeline Register Optimization
[23:55:11] Phase 3.6 Fast Optimization
[23:55:11] Phase 4 Post Placement Optimization and Clean-Up
[23:55:11] Phase 4.1 Post Commit Optimization
[23:55:41] Phase 4.1.1 Post Placement Optimization
[23:55:41] Phase 4.1.1.1 BUFG Insertion
[23:55:41] Phase 1 Physical Synthesis Initialization
[23:55:41] Phase 4.1.1.2 Post Placement Timing Optimization
[23:56:11] Phase 4.2 Post Placement Cleanup
[23:56:11] Phase 4.3 Placer Reporting
[23:56:11] Phase 4.3.1 Print Estimated Congestion
[23:56:11] Phase 4.4 Final Placement Cleanup
[23:57:11] Finished 4th of 6 tasks (FPGA logic placement). Elapsed time: 00h 05m 00s

[23:57:11] Starting logic routing..
[23:57:11] Phase 1 Build RT Design
[23:57:11] Phase 2 Router Initialization
[23:57:11] Phase 2.1 Fix Topology Constraints
[23:57:11] Phase 2.2 Pre Route Cleanup
[23:57:11] Phase 2.3 Global Clock Net Routing
[23:57:11] Phase 2.4 Update Timing
[23:57:41] Phase 3 Initial Routing
[23:57:41] Phase 3.1 Global Routing
[23:58:11] Phase 4 Rip-up And Reroute
[23:58:11] Phase 4.1 Global Iteration 0
[00:09:43] Phase 4.2 Global Iteration 1
[00:10:13] Phase 4.3 Global Iteration 2
[00:10:43] Phase 5 Delay and Skew Optimization
[00:10:43] Phase 5.1 Delay CleanUp
[00:10:43] Phase 5.1.1 Update Timing
[00:10:43] Phase 5.2 Clock Skew Optimization
[00:10:43] Phase 6 Post Hold Fix
[00:10:43] Phase 6.1 Hold Fix Iter
[00:10:43] Phase 6.1.1 Update Timing
[00:10:43] Phase 7 Route finalize
[00:10:43] Phase 8 Verifying routed nets
[00:10:43] Phase 9 Depositing Routes
[00:11:14] Phase 10 Resolve XTalk
[00:11:14] Phase 11 Route finalize
[00:11:14] Phase 12 Post Router Timing
[00:11:14] Finished 5th of 6 tasks (FPGA routing). Elapsed time: 00h 14m 02s