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使用VCS对Verilog/System Verilog进行单步调试的步骤

article 2025/2/4 21:44:30

Verilog单步调试：

System Verilog进行单步调试的步骤如下：

1. 编译设计
使用`-debug_all`或`-debug_pp`选项编译设计，生成调试信息。

我的4个文件：

1.led.v

module led(
	input clk,
	input rst_n,

	output reg led
);

reg [7:0] cnt;

always @ (posedge clk)
begin
	if(!rst_n)
		cnt <= 0;
	else if(cnt >= 10)
		cnt <= 0;
	else 
		cnt <= cnt + 1;
end

always @ (posedge clk)
begin
	if(!rst_n)
		led <= 0;
	else if(cnt == 10)
		led <= !led;
end

endmodule

2.led_tb.v

`timescale 1ns / 1ps

module led_tb;

// Parameters
parameter CLK_PERIOD = 10; // Clock period in ns

// Inputs
reg clk;
reg rst_n;

// Outputs
wire led;

// Instantiate the Unit Under Test (UUT)
led uut (
    .clk(clk), 
    .rst_n(rst_n), 
    .led(led)
);

// Clock generation
initial begin
    clk = 0;
    forever # (CLK_PERIOD/2) clk = ~clk;
end

initial	begin
	    $fsdbDumpfile("tb.fsdb");//这个是产生名为tb.fsdb的文件
	    $fsdbDumpvars;
end

// Test cases
initial begin
    // Initialize inputs
    rst_n = 0;
    # (CLK_PERIOD*2); // Wait for a few clock cycles

    // Test case 1: Reset active low
    rst_n = 0;
    # (CLK_PERIOD*10);
    $display("Test case 1: After reset, led = %b", led); // Expected: led = 0

    // Test case 2: Reset released, cnt < 10
    rst_n = 1;
    # (CLK_PERIOD*5);
    $display("Test case 2: After reset release, led = %b", led); // Expected: led = 0

    // Test case 3: cnt reaches 10, led toggles
    # (CLK_PERIOD*5);
    $display("Test case 3: After cnt reaches 10, led = %b", led); // Expected: led = 1

    // Finish simulation
    $finish;
end

3.Makefile

#------------------------------------------------------------------------------------------
FSDB_FILE = tb.fsdb
comp  : clean vcs
#------------------------------------------------------------------------------------------

vcs   :
	vcs  \
              -f filelist.f  \
              -timescale=1ns/1ns \
              -fsdb  -full64  -R  +vc  +v2k  -sverilog  -debug_all  \
              -P ${LD_LIBRARY_PATH}/novas.tab  ${LD_LIBRARY_PATH}/pli.a  \
              |  tee  vcs.log  &
#------------------------------------------------------------------------------------------
verdi  :
	 verdi -f filelist.f -ssf $(FSDB_FILE) &
#------------------------------------------------------------------------------------------
clean  :
	 rm  -rf  *~  core  csrc  simv*  vc_hdrs.h  ucli.key  urg* *.log  novas.* *.fsdb* verdiLog  64* DVEfiles *.vpd
#------------------------------------------------------------------------------------------