systemverilog中的循环（loop）

什么是循环？

        循环是一段会反复执行的代码。循环中通常包含一个条件语句，以便在条件变为真时能够终止循环。如果循环一直运行下去，那么仿真就会无限期地停滞。 SystemVerilog中不同类型的循环结构如下表所示。

1 forever 

        这是一个无限循环，就像while (1)那样。请注意，除非你在forever块内部包含一个时间延迟来推进仿真时间，否则你的仿真将会卡住（停滞）。        

module tb;

  // This initial block has a forever loop which will "run forever"
  // Hence this block will never finish in simulation
  initial begin
    forever begin
      #5 $display ("Hello World !");
    end
  end

  // Because the other initial block will run forever, our simulation will hang!
  // To avoid that, we will explicity terminate simulation after 50ns using $finish
  initial
    #50 $finish;
endmodule




//-----------Simulation Log-----------//
ncsim> run
Hello World !
Hello World !
Hello World !
Hello World !
Hello World !
Hello World !
Hello World !
Hello World !
Hello World !
Simulation complete via $finish(1) at time 50 NS + 0

2 repeat

        用于将一个代码块中的语句重复执行特定的次数。下面展示的示例将会把消息显示 5 次，然后继续执行剩余的代码。

module tb;

  	// This initial block will execute a repeat statement that will run 5 times and exit
	initial begin

        // Repeat everything within begin end 5 times and exit "repeat" block
		repeat(5) begin
			$display ("Hello World !");
		end
	end
endmodule


//-----------Simulation Log-----------//
ncsim> run
Hello World !
Hello World !
Hello World !
Hello World !
Hello World !
ncsim: *W,RNQUIE: Simulation is complete.

3 while

3.1语法

while (<condition>) begin
	// Multiple statements
end

        如果你了解Verilog/C语言的话，对此应该已经知晓了。只要条件为真，它就会重复执行代码块。下面的例子计数器最初为零，并且会不断递增，直至其达到10为止。

3.2示例

module tb;
 bit clk;

  always #10 clk = ~clk;
  initial begin
  	bit [3:0] counter;

    $display ("Counter = %0d", counter);      // Counter = 0
  	while (counter < 10) begin
    	@(posedge clk);
    	counter++;
        $display ("Counter = %0d", counter);      // Counter increments
  	end
  	$display ("Counter = %0d", counter);      // Counter = 10
    $finish;
end
endmodule

//-----------Simulation Log-----------//
ncsim> run
Counter = 0
Counter = 1
Counter = 2
Counter = 3
Counter = 4
Counter = 5
Counter = 6
Counter = 7
Counter = 8
Counter = 9
Counter = 10
Counter = 10
Simulation complete via $finish(1) at time 190 NS + 0

4 for

        与Verilog/C语言类似，这允许你在同一行中指定起始值、条件以及增量表达式。

module tb;
 bit clk;

  always #10 clk = ~clk;
  initial begin
  	bit [3:0] counter;

    $display ("Counter = %0d", counter);      // Counter = 0
  	for (counter = 2; counter < 14; counter = counter + 2) begin
    	@(posedge clk);
    	$display ("Counter = %0d", counter);      // Counter increments
  	end
    $display ("Counter = %0d", counter);      // Counter = 14
    $finish;
  end
endmodule

//-----------Simulation Log-----------//
ncsim> run
Counter = 0
Counter = 2
Counter = 4
Counter = 6
Counter = 8
Counter = 10
Counter = 12
Counter = 14
Simulation complete via $finish(1) at time 110 NS + 0

5 do while

5.1语法

do begin
	// Multiple statements
end while (<condition>);

        这会先执行代码，然后检查条件，以确定是否应该再次执行该代码。

5.2示例

module tb;
 bit clk;

  always #10 clk = ~clk;
  initial begin
  	bit [3:0] counter;

    $display ("Counter = %0d", counter);      // Counter = 0
		do begin
			@ (posedge clk);
			counter ++;
          $display ("Counter = %0d", counter);      // Counter increments
        end while (counter < 5);
    $display ("Counter = %0d", counter);      // Counter = 14
    $finish;
  end
endmodule
//-----------Simulation Log-----------//
ncsim> run
Counter = 0
Counter = 1
Counter = 2
Counter = 3
Counter = 4
Counter = 5
Counter = 5
Simulation complete via $finish(1) at time 90 NS + 0

5.1while和do while区别

        while循环和do while循环都是循环结构，只要给定的条件为真，它们就会执行给定的语句集。 `while`循环首先检查条件是否为真，如果为真，则执行语句。如果条件为假，循环就会立即结束。 `do while`循环则首先执行一次语句，然后检查条件是否为真。如果条件为真，就会重复执行语句集，直到条件变为假。如果条件为假，循环就会立即结束。 所以，二者之间的区别在于，`do while`循环至少会执行一次语句集。  

        语法上的区别

while (<condition>) begin
	// Multiple statements
end

do begin
	// Multiple statements
end while (<condition>);

6 foreach

        这非常适合用于遍历数组变量，因为你无需查找数组大小、设置一个初始值为0且在每次迭代时递增直至达到数组大小减1的变量。

module tb_top;
   bit [7:0] array [8];   // Create a fixed size array

   initial begin

      // Assign a value to each location in the array
      foreach (array [index]) begin
         array[index] = index;
      end

      // Iterate through each location and print the value of current location
      foreach (array [index]) begin
         $display ("array[%0d] = 0x%0d", index, array[index]);
      end
   end
endmodule
//-----------Simulation Log-----------//
ncsim> run
array[0] = 0x0
array[1] = 0x1
array[2] = 0x2
array[3] = 0x3
array[4] = 0x4
array[5] = 0x5
array[6] = 0x6
array[7] = 0x7
ncsim: *W,RNQUIE: Simulation is complete.