经典电荷泵/Charge pump——1998.JSSC

电路结构

工作原理

M3 and M4 are the series switches, and M5, M6 switch to the highest voltage. If M5 and M6 are missing, having a large capacitor is of absolute necessity, because must always stay between 2 V_in and 2V_in - U_j to avoid switching on the vertical bipolar ( U_j: junction potential).
With M5 and M6 included, C_out need not be large since the voltage drop at the output can be greater than U_j without affecting the charge-pump efficiency.
The capacitor C_B (Fig. 5) can be small, but it is still necessary to preserve the bulk potential when switching.
使用PMOS串行开关的原因：减小V_T。
使用PMOS串行开关产生的问题：reverse bias of the junctions。

效率分析（包含V_OUT计算方法）

Using bulk switching technique, the power efficiency is limited only by the losses of the source resistance R_s( in Fig. 6) and the switching losses.
Neglecting the resistance of the switches, the source resistance is given by

The factor 2 comes from the two capacitors C₁ and C₂ (Fig. 1), which act at each phase of the clock.
It was also assumed that the voltage drop of M1 through M4 is negligible.

where E_L is the energy delivered to load

and E_S is the energy loss

Here, ΔV_OUT is the drop due to R_S, C_S is the total stray capacitances of the circuit, and R_L is the load resistor. V_OUT is therefore the output of the voltage divider between R_S and R_L(Fig. 6)


则有

同理


故而在仿真过程中，无论是增加M1、M2的尺寸，或者是M3、M4的尺寸，都会因增加杂散电容而使V_OUT有不同程度的减小。
The total stray capacitance is assumed to be a fixed fraction α of the pump capacitor which represent its parasitics

the power efficiency maximum is reached for

使用非重叠开关的必要性

At high frequencies, the resistance of the switches and the time needed to switch between the states is not negligible because nonoverlapping switching is mandatory for high efficiency. This time depends on how the command signals are generated, and it can be a few nanoseconds, which is not negligible at frequencies above 10 MHz. The resulting time T_ON needed to transfer the charges is

Ref

[1] P. Favrat, P. Deval, and M. J. Declercq, “A high-efficiency CMOS voltage doubler,” IEEE J. Solid-State Circuits, vol. 33, no. 3, pp. 410–416, Mar. 1998, doi: 10.1109/4.661206.