[Mac + Icarus Verilog + gtkwave] Mac运行Verilog及查看波形图

1. MAC安装环境

1. 1 Icarus Verilog 编译

使用HomeBrew安装iVerilog (icarus-verilog)：

brew install icarus-verilog

1. 2 gtkwave 查看波形

brew install --HEAD randomplum/gtkwave/gtkwave

2. 安装遇到的问题

2. 1 macOS cannot verify that this app is free from malware

• Install the app anyway: If you downloaded an app from a trusted source but still can’t open it because of the “macOS cannot verify that this app is free from malware” error, you can try installing the app anyway. To do this, hold down Control and click on the app, then select “Open” from the context menu.
• Redownload the app: If the digital signature of the app is invalid or corrupted, you can try redownloading the app from the developer’s website.
• Use a different app: If you can’t get the app to work, consider using a different app that provides similar functionality.

2. 2 gtkwave-bin is not compatible with macOS 14 or later

This version of “gtkwave-bin” is not compatible with macOS 14 or later and needs to be updated. Contact the app developer for more information.

brew uninstall gtkwave
brew untap randomplum/gtkwave
brew install --HEAD randomplum/gtkwave/gtkwave

• 参考：Not Compatible with macOS 14 #2517

3. 运行示例

3. 1 源代码

• simple_circuit.v

module	simple_circuit(input a, input b, output y);  
    assign y = a & b;
endmodule

• test_bench.v

module	test_bench;
    reg		a, b;
    wire	y;

    // 实例化被测试单元。这行代码用于实例化一个名为 simple_circuit 的模块，并将其连接到测试平台中的信号。uut是该实例的名称，表示 "Unit Under Test"（被测试单元）。
    simple_circuit	uut (.a(a), .b(b), .y(y));

    // 应用输入
    initial	begin
        $dumpfile("./out/output_vcd.vcd");
        $dumpvars;

        a = 0; b = 0;
        #10 a = 0; b = 1;
        #10 a = 1; b = 0;
        #10 a = 1; b = 1;
        #10 $finish;
    end
endmodule

3. 2 编译Verilog

iverilog -o ./out/output_exe test_bench.v simple_circuit.v

这条命令使用 iverilog 编译器将 test_bench.v 和 simple_circuit.v 文件编译成一个可执行的仿真文件，并将其输出到 ./out/output_exe。

3. 3 生成.vcd文件

vvp ./out/output_exe

• 这条命令使用vvp仿真器运行之前生成的 ./out/output_exe 仿真文件。运行过程中，如果 Verilog 代码中包含生成波形文件的指令（如 $dumpfile和 $dumpvars），将会生成一个 .vcd 文件（波形文件）。
• vvp的全称是 Verilog Procedural Processor。它是Icarus Verilog仿真器的一部分，用于执行由iverilog编译器生成的仿真文件。

3. 3 查看波形

gtkwave out/output_vcd.vcd

3. 4 脚本运行

• run.sh

echo "Running the script >>>"

echo "1.Compiling the verilog code: "
iverilog -o ./out/output_exe test_bench.v simple_circuit.v

echo "2.Running the executable: "
vvp ./out/output_exe

echo "3.Generating the wave form: "
gtkwave out/output_vcd.vcd

• 然后，添加执行权限，再执行该脚本：

chmod +x run.sh
./run.sh

参考

• hello-verilog
• How to fix “macOS cannot verify that this app is free from malware” error
• Mac上进行Verilog仿真