1. uboot阶段无法控制PK
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
index 7e9f34a79e..d81a7c4fcd 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -27,7 +27,8 @@
#define SUNXI_GPIO_G 6
#define SUNXI_GPIO_H 7
#define SUNXI_GPIO_I 8
-#define SUNXI_GPIO_J 10
+#define SUNXI_GPIO_J 9
+#define SUNXI_GPIO_K 10
enum io_pow_mode_e {
IO_MODE_1_8_V = 0,
@@ -56,7 +57,7 @@ enum pin_e {
* You should fix up the padding in struct sunxi_gpio_reg below if you
* change this.
*/
-#define SUNXI_GPIO_BANKS 9
+#define SUNXI_GPIO_BANKS 11
/*
* sun6i/sun8i and later SoCs have an additional GPIO controller (R_PIO)
@@ -98,9 +99,26 @@ struct sunxi_gpio_reg {
struct sunxi_gpio_int gpio_int;
};
+#ifdef CONFIG_MACH_SUN55IW3
+#define SUNXI_PK_BASE 0x2000500
+#define BANK_TO_GPIO(bank) \
+ ({\
+ struct sunxi_gpio *pio; \
+ if (bank == 10) { \
+ pio = &((struct sunxi_gpio_reg *)SUNXI_PK_BASE)->gpio_bank[0]; \
+ } else if ((bank) < SUNXI_GPIO_L) { \
+ pio = &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank]; \
+ } else { \
+ pio = &((struct sunxi_gpio_reg *)SUNXI_R_PIO_BASE)->gpio_bank[(bank) - SUNXI_GPIO_L]; \
+ } \
+ pio; \
+ })
+
+#else
#define BANK_TO_GPIO(bank) (((bank) < SUNXI_GPIO_L) ? \
&((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank] : \
&((struct sunxi_gpio_reg *)SUNXI_R_PIO_BASE)->gpio_bank[(bank) - SUNXI_GPIO_L])
+#endif
#define GPIO_BANK(pin) ((pin) >> 5)
#define GPIO_NUM(pin) ((pin) & 0x1f)
@@ -162,6 +180,8 @@ struct sunxi_gpio_reg {
#define SUNXI_GPIO_G_NR 32
#define SUNXI_GPIO_H_NR 32
#define SUNXI_GPIO_I_NR 32
+#define SUNXI_GPIO_J_NR 32
+#define SUNXI_GPIO_K_NR 32
#define SUNXI_GPIO_L_NR 32
#define SUNXI_GPIO_M_NR 32
2.KERNEL内无法控制PK
bsp
Subject: [PATCH] support ppu always on
diff --git a/drivers/pm_domain/pck600_domains.c b/drivers/pm_domain/pck600_domains.c
index ec48b3c..33f37fc 100644
--- a/drivers/pm_domain/pck600_domains.c
+++ b/drivers/pm_domain/pck600_domains.c
@@ -202,8 +202,11 @@
const struct sunxi_domain_info *pd_info;
struct sunxi_pm_domain *pd;
u32 id;
+ bool is_always_on;
int error;
+ is_always_on = of_property_read_bool(node, "ppu-always-on");
+
error = of_property_read_u32(node, "reg", &id);
if (error) {
dev_err(pmu->dev,
@@ -245,6 +248,7 @@
pd->genpd.power_on = sunxi_pd_power_on;
pd->genpd.attach_dev = sunxi_pd_attach_dev;
pd->genpd.detach_dev = sunxi_pd_detach_dev;
+ pd->genpd.flags = (is_always_on) ? GENPD_FLAG_ALWAYS_ON : 0;
pm_genpd_init(&pd->genpd, NULL, false);
pmu->genpd_data.domains[id] = &pd->genpd;
---
drivers/pinctrl/pinctrl-sunxi.h | 31 +++++++++++++++++++++++--------
1 file changed, 23 insertions(+), 8 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-sunxi.h b/drivers/pinctrl/pinctrl-sunxi.h
index 565454fb5..4f698c231 100644
--- a/drivers/pinctrl/pinctrl-sunxi.h
+++ b/drivers/pinctrl/pinctrl-sunxi.h
@@ -94,6 +94,9 @@
#define SUNXI_PINCFG_TYPE_FUNC (PIN_CONFIG_END - 2)
#define SUNXI_PINCFG_TYPE_DAT (PIN_CONFIG_END - 1)
#endif
+
+#define SUN55IW3_PK_BASE 0x0500
+
enum sunxi_desc_bias_voltage {
BIAS_VOLTAGE_NONE,
/*
@@ -278,11 +281,26 @@ struct sunxi_pinctrl {
* The following functions calculate from the pin number the register
* and the bit offset that we should access.
*/
+
+static inline u32 sunxi_pinctrl_recalc_offset(enum sunxi_pinctrl_hw_type hw_type, u8 bank)
+{
+#ifdef CONFIG_ARCH_SUN55IW3
+ /* In a523 , the offset of PK does not meet the general rules, it starts directly from 0x500 */
+ if (bank != 10)
+ return bank * sunxi_pinctrl_hw_info[hw_type].bank_mem_size +
+ sunxi_pinctrl_hw_info[hw_type].initial_bank_offset;
+ else
+ return SUN55IW3_PK_BASE;
+#else
+ return bank * sunxi_pinctrl_hw_info[hw_type].bank_mem_size +
+ sunxi_pinctrl_hw_info[hw_type].initial_bank_offset;
+#endif
+}
+
static inline u32 sunxi_mux_reg(u16 pin, enum sunxi_pinctrl_hw_type hw_type)
{
u8 bank = pin / PINS_PER_BANK;
- u32 offset = bank * sunxi_pinctrl_hw_info[hw_type].bank_mem_size +
- sunxi_pinctrl_hw_info[hw_type].initial_bank_offset;
+ u32 offset = sunxi_pinctrl_recalc_offset(hw_type, bank);
offset += sunxi_pinctrl_hw_info[hw_type].mux_regs_offset;
offset += pin % PINS_PER_BANK / MUX_PINS_PER_REG * 0x04;
return round_down(offset, 4);
@@ -297,8 +315,7 @@ static inline u32 sunxi_mux_offset(u16 pin)
static inline u32 sunxi_data_reg(u16 pin, enum sunxi_pinctrl_hw_type hw_type)
{
u8 bank = pin / PINS_PER_BANK;
- u32 offset = bank * sunxi_pinctrl_hw_info[hw_type].bank_mem_size +
- sunxi_pinctrl_hw_info[hw_type].initial_bank_offset;
+ u32 offset = sunxi_pinctrl_recalc_offset(hw_type, bank);
offset += sunxi_pinctrl_hw_info[hw_type].data_regs_offset;
offset += pin % PINS_PER_BANK / DATA_PINS_PER_REG * 0x04;
return round_down(offset, 4);
@@ -313,8 +330,7 @@ static inline u32 sunxi_data_offset(u16 pin)
static inline u32 sunxi_dlevel_reg(u16 pin, enum sunxi_pinctrl_hw_type hw_type)
{
u8 bank = pin / PINS_PER_BANK;
- u32 offset = bank * sunxi_pinctrl_hw_info[hw_type].bank_mem_size +
- sunxi_pinctrl_hw_info[hw_type].initial_bank_offset;
+ u32 offset = sunxi_pinctrl_recalc_offset(hw_type, bank);
offset += sunxi_pinctrl_hw_info[hw_type].dlevel_regs_offset;
offset += pin % PINS_PER_BANK / sunxi_pinctrl_hw_info[hw_type].dlevel_pins_per_reg * 0x04;
return round_down(offset, 4);
@@ -329,8 +345,7 @@ static inline u32 sunxi_dlevel_offset(u16 pin, enum sunxi_pinctrl_hw_type hw_typ
static inline u32 sunxi_pull_reg(u16 pin, enum sunxi_pinctrl_hw_type hw_type)
{
u8 bank = pin / PINS_PER_BANK;
- u32 offset = bank * sunxi_pinctrl_hw_info[hw_type].bank_mem_size +
- sunxi_pinctrl_hw_info[hw_type].initial_bank_offset;
+ u32 offset = sunxi_pinctrl_recalc_offset(hw_type, bank);
offset += sunxi_pinctrl_hw_info[hw_type].pull_regs_offset;
offset += pin % PINS_PER_BANK / PULL_PINS_PER_REG * 0x04;
return round_down(offset, 4);
--
2.22.0
dts
diff --git a/configs/pro1/linux-5.15/board.dts b/configs/pro1/linux-5.15/board.dts
index 9c75b09..16f3fd0 100755
--- a/configs/pro1/linux-5.15/board.dts
+++ b/configs/pro1/linux-5.15/board.dts
@@ -2026,6 +2026,23 @@
cpu-supply = <®_tcs0>;
};
+&pd1 {
+ /* pk */
+ pd1_vi@A523_PCK_VI {
+ ppu-always-on;
+ };
+
+ /* pd */
+ pd1_vo0@A523_PCK_VO0 {
+ ppu-always-on;
+ };
+
+ /* pj */
+ pd1_vo1@A523_PCK_VO1 {
+ ppu-always-on;
+ };
+};
+
&dsufreq {
dsu-supply = <®_dcdc1>;
};
