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DC 使用记录

article 2024/9/16 19:37:15

前言

不使用change_name时，DC自动生成的.v网表文件会有许多反斜杠之类的命名，使用change_name，可以改变这种情况

1. change_name

1.1 执行

define_name_rules simple_names -allowed "A-Za-z0-9_" \
  -last_restricted "_" \
 -first_restricted "_" \
  -map { {{"\*cell\*","U"}, {"*-return","RET"}} }
 
change_name -rules simple_names -hierarchy

1.2 对比

执行前：
在这里插入图片描述
执行后：

2. elaboration

内容来源：https://ivlsi.com/physical-synthesis/

原文这样写道：2. Elaborate

As we read the RTL and we have only logical information in Boolean expressions, the very first thing tool does is make the building blocks as per the logic present in the RTL. Logically, now tool understands the logic hierarchy and input output of the different hierarchy levels inside the design. The second step tool does is map these building blocks with the inbuilt tool library. These cells are known as GTECH cells. The GTECH cells are technology independent as these are tool inbuilt. RTL codes are mostly written in Boolean expressions. At this stage, these Boolean expressions are converted into cell level using the inbuilt cells.

During elaboration, tool looks if the design and the hierarchy inside the design are unique or not> If unique, then only tool will proceed for further run. Once the run proceeds further, tool looks whether there are any unresolved reference in the design. If no unresolved reference, then tool proceeds further otherwise run stops. In this case, we need to debug the unresolved reference and get the RTL corrected.

简单讲，elaboration会进行如下操作，即工具会先将RTL代码读入，分析代码的层次结构，接着将其link成工具内部自带的工艺库（GTECH cells），link完毕后，工作会对相同的cells进行重命名以避免冲突，最后工具会对设计进行唯一化检查。