基于FPGA的无人机控制系统

drone_control.xdc

• 约束文件
  tcl

约束文件 (drone_control.xdc)

时钟约束

create_clock -name sys_clk -period 10.000 -waveform {0 5} [get_ports clk]

引脚约束

set_property PACKAGE_PIN L17 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports clk]

set_property PACKAGE_PIN M16 [get_ports rst]
set_property IOSTANDARD LVCMOS33 [get_ports rst]

set_property PACKAGE_PIN N15 [get_ports manual_mode]
set_property IOSTANDARD LVCMOS33 [get_ports manual_mode]

set_property PACKAGE_PIN P15 [get_ports low_battery]
set_property IOSTANDARD LVCMOS33 [get_ports low_battery]

set_property PACKAGE_PIN R15 [get_ports loss_of_control]
set_property IOSTANDARD LVCMOS33 [get_ports loss_of_control]

set_property PACKAGE_PIN T15 [get_ports pwm_signal_roll]
set_property IOSTANDARD LVCMOS33 [get_ports pwm_signal_roll]

set_property PACKAGE_PIN U15 [get_ports pwm_signal_pitch]
set_property IOSTANDARD LVCMOS33 [get_ports pwm_signal_pitch]

set_property PACKAGE_PIN V15 [get_ports pwm_signal_yaw]
set_property IOSTANDARD LVCMOS33 [get_ports pwm_signal_yaw]

set_property PACKAGE_PIN W15 [get_ports emergency_land]
set_property IOSTANDARD LVCMOS33 [get_ports emergency_land]
2.
modelsim.ini

• ModelSim仿真配置文件
  ini
  [Library]
  xil_defaultlib=work
  xpm=xpm
  unisims_ver=unisims_ver
  unimacro_ver=unimacro_ver
  secureip=secureip

[Source]
xil_defaultlib=work
xpm=xpm
unisims_ver=unisims_ver
unimacro_ver=unimacro_ver
secureip=secureip

[Simulation]
Waveform=wave.do
3.
build.tcl

• 综合和实现脚本
  tcl

综合和实现脚本 (build.tcl)

设置项目名称和路径

set project_name “drone_control”
set project_dir “./”
set top_module “drone_control”

创建项目

create_project $project_name $project_dir -part xc7z020clg400-1

添加源文件

add_files -fileset sources_1 {
src/hdl/imu_interface.v
src/hdl/pid_controller.v
src/hdl/motor_driver.v
src/hdl/flight_mode_controller.v
src/hdl/safety_mechanisms.v
src/hdl/drone_control.v
}

添加约束文件

add_files -fileset constrs_1 src/constraints/drone_control.xdc

更新编译顺序

update_compile_order -fileset sources_1

合成设计

synth_design -top $top_module -part xc7z020clg400-1

写入合成报告

write_checkpoint -force $projec{t}_{d}ir/$project_name_synth.dcp

实现设计

opt_design
place_design
route_design

写入实现报告

write_checkpoint -force p r o j e c t d i r / project_dir/