#systemverilog# 关于 randomize(a) 却报 b 失败的疑问
在函数中 ，重新约束了类内的随机变量。请看如下代码：
`timescale 1ns/1ps
`include "uvm_macros.svh"
import uvm_pkg::*;
class my_obj1 extends uvm_test;
`uvm_component_utils(my_obj1)
rand int src;
rand int dst;
constraint dst_c {
dst inside {[7:9]};
}
function new(string name = "my_obj1" , uvm_component parent = null );
super.new(name, parent);
endfunction // new
extern virtual function print ();
virtual task run_phase(uvm_phase phase);
super.run_phase(phase);
endtask
endclass //
function my_obj1::print();
randomize (src) with {(src) inside {[5:5]};} ;
endfunction
module tb();
import uvm_pkg::*;
`include "uvm_macros.svh"
initial begin